1. Field of the Invention
The present invention relates to a semiconductor technique, and particularly to a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor. Particularly, the present invention relates to a method for fabricating a high density trench gate type power device.
2. Description of the Prior Art
Generally, the power device based on the MOS (metal oxide semiconductor) technology is classified into: a VDMOS (vertical double-diffused metal oxide semiconductor) in which the source-gate-drain are disposed in the vertical direction; and an LDMOS (lateral double-diffused metal oxide semiconductor) in which the source-gate-drain are disposed in the horizontal direction.
The VDMOS can accommodate a larger electric current than the LDMOS, and therefore, it is used as a large current power device. Further, the VDMOS is classified in accordance with its type into a planar gate type and a trench gate type.
The trench gate type power device has the disadvantage that the fabricating process is complicated, because a trench has to be etched in a silicon substrate, and because a good quality gate oxide layer has to be grown. However, it can build a larger number of devices per unit area compared with the planar gate type power device, and therefore, the on-resistance which is an important factor of a power device can be lowered. Further, it can accommodate a large current with a low driving voltage. Therefore, it is the present trend that the use of the power device is being transferred from the planar gate type power device to the trench gate type power device.
FIG. 1 illustrates the layout of a trench gate type power device. Referring to this drawing, the trench gate type power device 100 is constituted such that a well 104 and a source 106 are defined across a trench gate 102. All the drawings hereinafter will be sectional views taken along a line A-B.
FIGS. 2A to 2C illustrate the fabricating process for the conventional N-channel trench gate type power device. This conventional fabricating process will be described in detail below.
First, as shown in FIG. 2A, an oxide layer 22 is grown upon an N.sup.- -epi-layer 21 /N.sup.+ silicon substrate 20. Then a P-well mask is used to etch a portion of the oxide layer 22 where a P-well is to be formed. Then a screen oxide layer 23 is grown upon the exposed N.sup.- -epi-layer 21 in a thickness of 400 .ANG.. Then an impurity ion implantation is carried out for forming a P-well, and then, a heat treatment is carried out, thereby forming a P-well 24 on the N.sup.- -epi-layer 21.
Then as shown in FIG. 2B, a source mask is used to form an N.sup.+ source 25, and then, an oxide layer 26 is deposited on the entire structure. Then a trench gate mask is used to etch a portion of the oxide layer 26 where a trench gate is to be formed. Then a hard mask is used on the patterned oxide layer 26 to form a trench which is deeper than the P-well. Then a gate oxide layer 27 is grown along the side wall of the trench, and then, a doped polysilicon film is deposited. Then a gate electrode mask is used on the polysilicon film to carry out an anisotropic etching, thereby forming a trench gate 28.
Under this condition, although there is not illustrated in the drawings, a pad for realizing a gate contact is formed on the edge region.
Then as shown in FIG. 2C, a field oxide layer 29 is deposited on the entire structure, and then, a gate and source electrode contact mask is used to selectively etch the oxide layer 29, thereby forming the gate and source electrode contact holes. Then a metal layer is deposited upon the entire structure, and then, a gate and source electrode mask is used to pattern the gate and source electrodes 30. Then a drain electrode 31 is formed on the rear face of the substrate.
As described above, in the conventional trench gate type power device fabricating process, there are required six masks including the P-well mask, the source mask, the trench gate mask, the gate electrode mask, the gate and source electrode contact mask, and the gate and source electrode mask. Further, in the case where P.sup.+ ions are implanted into the source region, another sheet of mask is additionally required.
Thus a large number of masks is required in the conventional fabricating process, and therefore, the fabricating process becomes complicated, while the fabricating cost is increased. Further, due to the increase in the number of the masking processes, align errors are induced, with the result that the realization of a high density is hindered, and that the yield is lowered. Due to this difficulty of realizing the high density, the on-resistance which is an important factor of the power device is degraded.